1. Field of the Invention
The present invention relates to a low-voltage triggering silicon-controlled rectifier (LVTSCR) and, more particularly, to a LVTSCR with a holding voltage that is greater than a dc bias voltage on a to-be-protected node.
2. Description of the Related Art
A silicon-controlled rectifier (SCR) is a device that provides an open circuit between a first node and a second node when the voltage across the first and second nodes is positive and less than a trigger voltage. When the voltage across the first and second nodes rises to be equal to or greater than the trigger voltage, the SCR provides a low-resistance current path between the first and second nodes. Further, once the low-resistance current path has been provided, the SCR maintains the current path as long as the voltage across the first and second nodes is equal to or greater than a holding voltage that is lower than the trigger voltage.
As a result of these characteristics, SCRs have been used to provide electro-static discharge (ESD) protection. When used for ESD protection, the first node becomes a to-be-protected node, and the second node becomes an output node. The SCR operates within an ESD protection window that has a maximum voltage defined by the destructive breakdown level of the to-be-protected node, and a minimum voltage (also known as a latch-up voltage) defined by any dc bias on the to-be-protected node. The trigger voltage of the SCR is then set to a value that is less than the maximum voltage of the window, while the holding voltage is set to a value that is greater than the minimum voltage of the window.
Thus, when the voltage across the to-be-protected node and the output node is less than the trigger voltage, the SCR provides an open circuit between the to-be-protected node and the output node. However, when the to-be-protected node receives a voltage spike that equals or exceeds the trigger voltage, such as when an ungrounded human-body contact occurs, the SCR provides a low-resistance current path from the to-be-protected node to the output node. In addition, once the ESD event has passed and the voltage on the to-be-protected node falls below the holding voltage, the SCR again provides an open circuit between the to-be-protected node and the output node.
FIG. 1 shows a cross-sectional view that illustrates a conventional SCR 100. As shown in FIG. 1, SCR 100 has a n-well 112 which is formed in a p-type semiconductor material 110, such as a substrate or a well, and a n+ region 114 and a p+ region 116 which are formed in n-well 112. N+ and p+ regions 114 and 116, in turn, are both connected to a to-be-protected node 120. As further shown in FIG. 1, SCR 100 also has a n+ region 122 and a p+ region 124 formed in semiconductor material 110. N+ and p+ regions 122 and 124, in turn, are both connected to an output node 126.
In operation, when the voltage across nodes 120 and 126 is positive and less than the trigger voltage, the voltage reverse biases the junction between n-well 112 and p-type material 110. The reverse-biased junction, in turn, blocks charge carriers from flowing from node 120 to node 126. However, when the voltage across nodes 120 and 126 is positive and equal to or greater than the trigger voltage, the reverse-biased junction breaks down due to avalanche multiplication.
The breakdown of the junction causes a large number of holes to be injected into material 110, and a large number of electrons to be injected into n-well 112. The increased number of holes increases the potential of material 110 in the region that lies adjacent to n+ region 122, and eventually forward biases the junction between material 110 and n+ region 122.
When the increased potential forward biases the junction, a npn transistor that utilizes n+ region 122 as the emitter, p-type material 110 as the base, and n-well 112 as the collector turns on. When turned on, n+ (emitter) region 122 injects electrons into (base) material 110. Most of the injected electrons diffuse through (base) material 110 and are swept from (base) material 110 into (collector) n-well 112 by the electric field that extends across the reverse-biased junction. The electrons in (collector) n-well 112 are then collected by n+ region 114.
A small number of the electrons injected into (base) material 110 recombine with holes in (base) material 110 and are lost. The holes lost to recombination with the injected electrons are replaced by holes injected into (base) material 110 by the broken-down reverse-biased junction and, as described below, by the collector current of a pnp transistor, thereby providing the base current.
The electrons that are injected and swept into n-well 112 also decrease the potential of n-well 112 in the region that lies adjacent to p+ region 116, and eventually forward bias the junction between p+ region 116 and n-well 112. When the decreased potential forward biases the junction between p+ region 116 and n-well 112, a pnp transistor formed from p+ region 116, n-well 112, and material 110 turns on.
When turned on, p+ emitter 116 injects holes into base 112. Most of the injected holes diffuse through (base) n-well 112 and are swept from (base) n-well 112 into (collector) material 110 by the electric field that extends across the reverse-biased junction. The holes in (collector) material 110 are then collected by p+ region 124.
A small number of the holes injected into (base) n-well 112 recombine with electrons in (base) n-well 112 and are lost. The electrons lost to recombination with the injected holes are replaced by electrons flowing into n-well 112 as a result of the broken-down reverse-biased junction, and n-well 112 being the collector of the npn transistor. Thus, a small part of the npn collector current forms the base current of the pnp transistor.
Similarly, as noted above, the holes swept into (collector) material 110 also provide the base current holes necessary to compensate for the holes lost to recombination with the diffusing electrons injected by n+ (emitter) region 122. Thus, a small part of the pnp collector current forms the base current of the npn transistor.
Thus, n+ region 122 injects electrons that provide both the electrons for the collector current of the npn transistor as well as the electrons for the base current of the pnp transistor. At the same time, p+ region 116 injects holes that provide both the holes for the collector current of the pnp transistor as well as the holes for the base current of the npn transistor.
One of the advantages of SCR 100 over other ESD protection devices, such as a grounded-gate MOS transistor, is the double injection provided by n+ region 122 and p+ region 116 of SCR 100. With double injection, SCR 100 provides current densities (after snapback) that are about ten times greater than the densities provided by a grounded-gate MOS device, thus increasing the ESD protection capability. (Protection capability can be defined as the required contact width of the structure required to protect from a given ESD pulse amplitude, or the maximum protected ESD pulse amplitude for a given contact width.) One of the disadvantages of SCR 100, however, is that a very large positive voltage, e.g., 50 volts, must be dropped across nodes 120 and 126 before the junction between p-type material 110 and n-well 112 breaks down. As a result, SCR 100 can not be used to protect devices, such as MOS transistors, that can be permanently damaged by much lower voltages, e.g., 15 volts.
One solution to this problem, known as a low-voltage triggering SCR (LVTSCR), incorporates a NMOS transistor into SCR 100. FIG. 2 shows a cross-sectional diagram that illustrates a conventional LVTSCR 200. LVTSCR 200 and SCR 100 are similar and, as a result, utilize the same reference numerals to designate the structures that are common to both devices.
As shown in FIG. 2, LVTSCR 200 differs from SCR 100 in that LVTSCR 200 has a n+ (drain) region 230 that is formed in both material 110 and n-well 112, and a channel region 232 that is defined between n+ (source) region 122 and n+ (drain) region 230. In addition, LVTSCR 200 includes a gate oxide layer 234 that is formed on material 110 over channel region 232, and a gate 236 that is formed on gate oxide layer 234. N+ (source and drain) regions 122 and 230, gate oxide layer 234, and gate 236 define a NMOS transistor 238 which is typically formed to be identical to the to-be-protected MOS transistors in the circuit.
In operation, when the voltage on the drain of a conventional NMOS transistor spikes up, the drain-to-substrate junction of the NMOS transistor breaks down, for example, at 7 volts, while the gate oxide layer that isolates the gate from the drain destructively breaks down at, for example, 10-15 volts.
Since NMOS transistor 238 is formed to be identical to the to-be-protected MOS transistors, the junction between n+ region 230 and material 110 breaks down at the same time that the to-be-protected MOS transistors experience junction break down as a result of an ESD pulse. Once the reverse-biased junction between region 230 and material 110 breaks down, the break down triggers LVTSCR 200 to operate the same as SCR 100.
Since junction break down occurs before the MOS transistors experience destructive gate oxide break down, LVTSCR 200 turns on before destructive gate oxide breakdown occurs, thereby protecting the MOS transistors. Thus, the junction break down voltage, which is less than the voltage level that causes destructive gate oxide break down, functions as the trigger voltage. In addition, other techniques, such as reducing the width of channel region 232, can be used to lower the trigger voltage so that the region 230 to material 110 junction breaks down before the to-be-protected MOS transistors experience junction break down.
Thus, LVTSCR 200 provides a SCR with a significantly lower turnon voltage that allows MOS transistors to be protected from ESD events with an SCR. One disadvantage of LVTSCR 200, however, is that LVTSCR 200 suffers from a holding voltage that is often less than the minimum (or latch-up) voltage of the ESD protection window. As a result, LVTSCRs are unattractive candidates for providing ESD protection to power supply pins.
When the minimum (or latch-up) voltage of the ESD protection window is equal to a dc bias, such as the power supply voltage, and the holding voltage is less than the minimum voltage, LVTSCR 200 can not turn off (thus latching up) after the ESD event has passed. Thus, power must be cycled after the ESD event.
For example, assume that node 120 is a power supply pin at 3.3 volts, node 126 is a ground pin, the junction breakdown voltages of the to-be-protected MOS transistors are 7.0 volts, and the holding voltage is 1.8 volts. In this example, LVTSCR 200 is turned off under normal operating conditions when the voltage on node 120 is 3.3 volts. When the voltage on node 120 spikes up to a value equal to or greater than the trigger voltage (7 volts in this example), LVTSCR 200 turns on, thereby protecting the MOS devices that receive power from node 120.
However, once the ESD event has passed, it takes only 1.8 volts on node 120 to keep LVTSCR 200 in this example turned on. Since the normal operating voltage on node 120 is 3.3 volts, LVTSCR 200 remains turned on (latched up) after the ESD event has passed. Thus, to provide ESD protection to lines with a dc bias, such as power supply lines, via a LVTSCR, there is a need for a LVTSCR with a holding voltage that is greater than the dc bias.
The present invention provides a low-voltage triggering silicon-controlled rectifier (LVTSCR) that increases the value of the holding voltage by inserting a voltage drop circuit between a to-be-protected node with a dc bias, such as a power supply node, and the emitter of the pnp transistor of the LVTSCR.
A low-voltage triggering silicon-controlled rectifier (LVTSCR) in accordance with the present invention is formed in a semiconductor material of a first conductivity type, and includes a well of a second conductivity type that is formed in the semiconductor material. The LVTSCR also includes a first region of the second conductivity type that is formed in the well, and a second region of the first conductivity type that is formed in the well. The first region is connected to a first node.
The LVTSCR further includes a third region of the second conductivity type that is formed in the semiconductor material, and a fourth region of the first conductivity type that is formed in the semiconductor material. The third and fourth regions are connected to a second node. The LVTSCR additionally includes a fifth region of the second conductivity type that is formed in the semiconductor material and the well, and a voltage drop circuit that is connected between the second region and the first node.
The present invention also includes a method for operating the LVTSCR that includes the steps of placing a first voltage on the first region, and a second voltage on the second region. The first and second voltages are different. In addition, the method includes the step of placing a third voltage on the third and fourth regions.
A better understanding of the features and advantages of the present invention will be obtained by reference to the following detailed description and accompanying drawings that set forth an illustrative embodiment in which the principles of the invention are utilize